1. Field of the Invention
The present invention relates to a failure analysis device and a failure analysis method, and particularly to an automatic failure analysis device and an automatic failure analysis method for examining chips having logic LSIs fabricated therein or chips having system LSIs having logic regions fabricated therein. The present invention relates also to a semiconductor device manufacturing method using the failure analysis method.
2. Description of the Background Art
In the failure analysis of semiconductor devices such as LSIs, light emission analysis is one of the most common analysis methods. In the light emission analysis, a light detecting device which can detect very weak photon-level light is used to detect very weak light emitted at leakage locations so as to determine the failure locations. This technique can be applied not only to analysis of leakage failures such as power-supply leakage, standby leakage, etc. but also to analysis of operation failures accompanied by leakage. The light emission analysis is indispensable analysis means particularly in identifying failure locations in logic LSIs or in logic regions of system LSIs in which electrical testing cannot successfully identify failure locations.
A conventional light emission analysis for examining logic LSIs is now described. FIG. 20 is a block diagram showing the structure of a conventional failure analysis device. The wafer 101 has a matrix of a plurality of chips to be tested (not shown). Each chip has a logic LSI fabricated therein. The wafer 101 is placed on a wafer stage 102.
A known probe card 105 is disposed to face toward the wafer surface of the wafer 101. The probe card 105 has a plurality of probes 106 for making contact with electrode pads formed on the chips. A light detecting device 107 is disposed near the wafer surface of the wafer 101. The light detecting device 107 is connected to a failure location analysis unit 108. The conventional failure analysis device also has a recording unit 103 connected to the probe card 105 and a main control unit 104 connected to the probe card 105 and the wafer stage 102.
FIG. 21 is a flowchart showing the procedure of light emission analysis using the conventional failure analysis device shown in FIG. 20. First, in the step SP7A, an operator enters measurement conditions into the failure analysis device. More specifically, the operator enters data D101 about conditions to be individually set into the main control unit 104, so as to specify a plurality of wafers to be tested among a plurality of wafers stored in a wafer cassette, to specify a plurality of chips to be tested among a plurality of chips formed on each wafer, to specify test conditions about the test pattern, voltage application, etc.
Next, in the step SP7B, the first wafer 101, or a wafer to be tested first among the plurality of wafers to be tested, is placed on the wafer stage 102. Next, in the step SP7C, the wafer stage 102 moves the wafer 101 on the basis of a control signal S101 provided from the main control unit 104 to align the first chip, or a chip to be tested first among the plurality of chips to be tested on the wafer 101, with the light detecting device 107. The probes 106 of the probe card 105 are then set into contact with given electrode pads formed on the chip.
Next, in the step SP7D, the probe card 105 applies a test pattern composed of a plurality of test vectors TB1 to TBn to the chip on the basis of a control signal S102 provided from the main control unit 104. Next, in the step SP7E, the probe card 105 sequentially detects quiescent power supply currents (Iddq) which flow when the individual test vectors TB1 to TBn are applied. The recording unit 103 then records the Iddq values I1 to In sequentially provided from the probe card 105.
Next, in the step SP7F, the operator refers to the Iddq values I1 to In recorded in the recording unit 103 to identify an abnormality occurrence vector. FIG. 22 is a diagram used to explain a method in which the operator identifies the abnormality occurrence vector. In the diagram, the horizontal axis shows the test vectors TB1 to TBn and the vertical axis shows the current value. The test vectors are sequentially applied upon each input of a clock and the logic state changes. A large switching current flows at the instant the logic state changes and then the current value settles in quiescent state. The power-supply current which flows in this quiescent state is the quiescent power supply current (Iddq). The waveform shown in FIG. 22 is recorded in the recording unit 103 and the operator refers to this waveform and specifies a test vector with which the Iddq value shows an abnormal value as the abnormality occurrence vector (the test vector TB3 in the example shown in FIG. 22).
Next, in the step SP7G, the operator enters data D102 about the specified abnormality occurrence vector into the main control unit 104. The probe card 105 then applies again the test pattern from the first test vector TB1 to the abnormality occurrence vector to the chip on the basis of a control signal S103 provided from the main control unit 104 and holds the state in which the abnormality occurrence vector is applied to the chip.
Next, in the step SP7H, the failure location on the chip is located through the light emission analysis. More specifically, with the abnormality occurrence vector applied to the chip, the light detecting device 107 detects light emission from the chip. The failure location analysis unit 108 then locates the failure location on the chip on the basis of data T about the location of the light emission provided from the light detecting device 107.
Next, in the step SP7I, the main control unit 104 checks whether the chip currently in alignment is the last chip. When the step SP7I provides a decision xe2x80x9cNO,xe2x80x9d the flow moves to the step SP7J, where the next chip is aligned. The operations in and after the step SP7D are then applied to the aligned chip.
When the decision of the step SP7I is xe2x80x9cYES,xe2x80x9d the flow goes to the step SP7K, where the main control unit 104 checks whether the wafer 101 currently placed on the wafer stage 102 is the last wafer. When the step SP7K shows xe2x80x9cNO,xe2x80x9d the flow moves to the step SP7L, where the next wafer is placed on the wafer stage 102. The operations in and after the step SP7C are then applied to that wafer.
When the decision made in the step SP7K is xe2x80x9cYES,xe2x80x9d the test is ended.
As explained above, the light emission analysis of logic LSIs requires that the light emission analysis be executed with the abnormality occurrence vector applied to the chip. However, with the conventional failure analysis device, the operator must refer to the current waveform recorded in the recording unit 103 to specify the abnormality occurrence vector.
Devices for automatically applying the light emission analysis to all or part of chips formed on a wafer include those disclosed in Japanese Patent Application Laid-Open Nos. 10-4128 (1998) and 10-223707 (1998), some of which are used in practice. However, these devices are designed to apply automatic light emission analysis to a plurality of chips under predetermined fixed conditions. Therefore these devices cannot be directly applied to the light emission analysis of logic LSIs in which the measurement conditions must be varied chip by chip because different abnormality occurrence vectors are specified among different chips.
According to a first aspect of the present invention, a failure analysis device comprises: a test pattern applying portion for applying a test pattern composed of a plurality of test vectors to a test target; an abnormality occurrence vector specifying portion for specifying an abnormality occurrence vector which can activate a failure present in the test target from among the test pattern on the basis of detected values of quiescent power supply currents which flow in the test target respectively when the plurality of test vectors are applied; and a failure location analysis portion for analyzing the location of the failure in the test target by detecting light emission from the test target with the abnormality occurrence vector applied to the test target.
Preferably, according to a second aspect, in the failure analysis device of the first aspect, the abnormality occurrence vector specifying portion specifies the abnormality occurrence vector on the basis of results of comparison between a given threshold and the detected values of the quiescent power supply currents.
Preferably, according to a third aspect, in the failure analysis device of the first aspect, the abnormality occurrence vector specifying portion specifies the abnormality occurrence vector on the basis of results of comparison between a given threshold and differences between normal values of the quiescent power supply currents which flow in the test target having no failure and the detected values of the quiescent power supply currents.
Preferably, according to a fourth aspect, in the failure analysis device of the first aspect, the test target is each of a plurality of semiconductor chips formed on a semiconductor wafer, and the abnormality occurrence vector specifying portion specifies the abnormality occurrence vector on the basis of results of comparison between a given threshold and differences between given reference values and the detected values of the quiescent power supply currents, and wherein the failure analysis device further comprises a reference value setting portion for setting the reference values by statistically processing the detected values of the quiescent power supply currents.
Preferably, according to a fifth aspect, the failure analysis device of the third or fourth aspect further comprises a failure number estimating portion for estimating the number of the failures present in the test target on the basis of the differences.
Preferably, according to a sixth aspect, the failure analysis device of the fourth aspect further comprises a failure number estimating portion for estimating the number of the failures present in the test target on the basis of the differences, and a display portion for displaying a wafer map which shows the number of the failures in each of the plurality of semiconductor chips, the wafer map being generated on the basis of the results of the estimation performed by the failure number estimating portion.
According to a seventh aspect of the present invention, a failure analysis device comprises: a failure number estimating portion for estimating the number of failures present in each of a plurality of semiconductor chips; a functional test device for carrying out a functional test about the plurality of semiconductor chips by using a test pattern generated on the basis of circuit information about the plurality of semiconductor chips, a test result selecting portion for selecting test results about semiconductor chips in which the number of the failures is estimated to be one from among a plurality of test results of the functional test about the plurality of semiconductor chips on the basis of the results of the estimation performed by the failure number estimating portion; and a failure node estimating portion for estimating failure nodes in the semiconductor chips on the basis of the test results selected by the test result selecting portion and a failure dictionary generated on the basis of the circuit information about the plurality of semiconductor chips.
Preferably, according to an eighth aspect, the failure analysis device of the seventh aspect further comprises a light emission analysis device for analyzing locations of the failures in the semiconductor chips by detecting light emission from the semiconductor chips, and a detailed analysis portion for analyzing in detail the locations of the failure nodes on the basis of the results of the analysis performed by the light emission analysis device and the results of the estimation performed by the failure node estimating portion.
According to a ninth aspect of the present invention, a failure analysis method comprises the steps of: (a) applying a test pattern composed of a plurality of test vectors to a test target; (b) specifying an abnormality occurrence vector which can activate a failure present in the test target from among the test pattern on the basis of detected values of quiescent power supply currents which flow in the test target when the plurality of test vectors are applied; and (c) analyzing the location of the failure in the test target by detecting light emission from the test target with the abnormality occurrence vector applied to the test target.
Preferably, according to a tenth aspect, in the step (b) of the failure analysis method of the ninth aspect, the abnormality occurrence vector is specified on the basis of results of comparison between a given threshold and the detected values of the quiescent power supply currents.
Preferably, according to an eleventh aspect, in the step (b) of the failure analysis method of the ninth aspect, the abnormality occurrence vector is specified on the basis of results of comparison between a given threshold and differences between normal values of the quiescent power supply currents which flow in the test target having no failure and the detected values of the quiescent power supply currents.
Preferably, according to a twelfth aspect, in the failure analysis method of the ninth aspect, the test target is each of a plurality of semiconductor chips formed on a semiconductor wafer, and in the step (b), the abnormality occurrence vector is specified on the basis of results of comparison between a given threshold and differences between given reference values and the detected values of the quiescent power supply currents, and wherein the failure analysis method further comprises a step (d) of setting the reference values by statistically processing the detected values of the quiescent power supply currents.
Preferably, according to a thirteenth aspect, the failure analysis method of the eleventh or twelfth aspect further comprises a step (e) of estimating the number of the failures present in the test target on the basis of the differences.
Preferably, according to a fourteenth aspect, the failure analysis method of the twelfth aspect further comprises the steps of (e) estimating the number of the failures present in the test target on the basis of the differences, and (f) displaying a wafer map which shows the number of the failures in each of the plurality of semiconductor chips, the wafer map being generated on the basis of the results of the estimation performed in the step (e).
According to a fifteenth aspect of the present invention, a failure analysis device comprises: a failure number estimating portion for estimating the number of failures present in each of a plurality of semiconductor chips; a functional test device for carrying out a functional test about the plurality of semiconductor chips by using a test pattern generated on the basis of circuit information about the plurality of semiconductor chips, a test result selecting portion for selecting test results about semiconductor chips in which the number of the failures is estimated to be one from among a plurality of test results of the functional test about the plurality of semiconductor chips on the basis of the results of the estimation performed by the failure number estimating portion; and a failure node estimating portion for estimating failure nodes in the semiconductor chips on the basis of the test results selected by the test result selecting portion and a failure dictionary generated on the basis of the circuit information about the plurality of semiconductor chips.
Preferably, according to a sixteenth aspect, the failure analysis device of the fifteenth aspect further comprises, a light emission analysis device for analyzing locations of the failures in the semiconductor chips by detecting light emission from the semiconductor chips, and a detailed analysis portion for analyzing in detail the locations of the failure nodes on the basis of the results of the analysis performed by the light emission analysis device and the results of the estimation performed by the failure node estimating portion.
A seventeenth aspect of the present invention is directed to a method of manufacturing a semiconductor device by using one of the failure analysis methods of the ninth to fourteenth aspects of the present invention.
According to the first aspect of the present invention, the abnormality occurrence vector specifying portion specifies the abnormality occurrence vector item by item. Therefore the efficiency of the failure analysis can be improved by realizing automatic wafer-level light emission analysis even when the tested items are chips having logic LSIs fabricated therein or chips having system LSIs having logic regions fabricated therein which require that the test vector applied during the light emission analysis be changed chip by chip.
According to the second aspect of the present invention, the abnormality occurrence vector specifying portion can automatically specify the abnormality occurrence vectors on the basis of the results of the comparison between the detected values of the quiescent power supply current and the given threshold.
According to the third aspect of the present invention, the abnormality occurrence vector specifying portion can automatically and accurately specify the abnormality occurrence vectors on the basis of the results of the comparison between the given threshold and the differences between the normal values of the quiescent power supply currents and their detected values.
According to the fourth aspect of the present invention, the given reference values can be automatically set by utilizing the test target semiconductor wafer, without performing simulation or actual measurement with normal chips.
According to the fifth aspect of the present invention, a wafer map showing the numbers of failures in the individual semiconductor chips can be generated on the basis of the results of the estimation performed by the failure number estimating portion.
According to the sixth aspect of the present invention, the distribution of failure locations in the wafer can be easily grasped visually by referring to the wafer map.
According to the seventh aspect of the present invention, the failure node estimating portion estimates failure nodes on the basis of the failure dictionary and the test results only about semiconductor chips for which the number of failures has been estimated to be one, so that the accuracy of the failure node diagnosis performed by the failure node estimating portion can be enhanced.
According to the eighth aspect of the present invention, the detailed analysis portion analyzes in detail the failure locations on the basis of a combination of the results of the analysis performed by the light emission analysis device and the results of the estimation performed by the failure node estimating portion, so that it can accurately locate the failure locations.
According to the ninth aspect of the present invention, in the step (b), the abnormality occurrence vector is specified item by item on the basis of the detected values of the quiescent power supply currents which flow in the test target. Therefore the efficiency of the failure analysis can be improved by realizing automatic wafer-level light emission analysis even when the tested items are chips having logic LSIs fabricated therein or chips having system LSIs having logic regions fabricated therein which require that the test vector applied during the light emission analysis be changed chip by chip.
According to the tenth aspect of the present invention, the abnormality occurrence vectors can be automatically specified on the basis of the results of the comparison between the detected values of the quiescent power supply currents and the given threshold.
According to the eleventh aspect of the present invention, the abnormality occurrence vectors can be automatically and accurately specified on the basis of the results of the comparison between the given threshold and the differences between the normal values of the quiescent power supply currents and their detected values.
According to the twelfth aspect of the present invention, the given reference values can be automatically set by utilizing the test target semiconductor wafer, without performing simulation or actual measurement with normal chips.
According to the thirteenth aspect of the present invention, a wafer map showing the numbers of failures in the individual semiconductor chips can be generated on the basis of the results of the estimation of the number of failures.
According to the fourteenth aspect of the present invention, the distribution of failure locations in the wafer can be easily grasped visually by referring to the wafer map.
According to the fifteenth aspect of the present invention, failure nodes are estimated on the basis of the failure dictionary and the test results only about semiconductor chips for which the number of failures has been estimated to be one, so that the accuracy of the failure node diagnosis in the step (d) can be enhanced.
According to the sixteenth aspect of the present invention, the failure locations are analyzed in detail on the basis of a combination of the results of the light emission analysis in the step (e) and the results of the estimation of the failure node in the step (d), so that the failure locations can be accurately located.
According to the seventeenth aspect of the present invention, the efficiency of manufacturing a semiconductor device can be improved.
The present invention has been made to solve the problem explained earlier, and an object of the present invention is to obtain a wafer-level failure analysis device and failure analysis method in which the light emission analysis can be automatically performed even when the tested chips have logic LSIs etc. fabricated therein.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.